Selective cache line allocation instruction execution and...

Details Selective cache line allocation instruction execution and... Selective cache line allocation instruction execution and...

2006-05-11

2008-08-05

Ellis, Kevin L (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07409502

ABSTRACT:
A processing system and method performs allocation of memory cache lines in response to a cache write miss. A processor receives a plurality of data processing instructions. A first store instruction for storing data in a system memory at a predetermined address is decoded by decoding a first specifier within the first store instruction. The first specifier determines an allocation policy for the first store instruction wherein the allocation policy determines whether to store data within the cache when the predetermined address is not within the cache. Additional store instructions are decoded. For example, a second specifier determines an allocation policy for a second store instruction. The specifier in each of the store instructions may be implemented in various forms to provide a policy indicator for each store instruction. No allocation policy may also be established on a per-access basis.

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