Segmented memory system employing different interleaving scheme

Details Segmented memory system employing different interleaving scheme Segmented memory system employing different interleaving scheme

1997-07-02

2000-04-11

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 5, 710128, G06F 1206

Patent

active

060498552

ABSTRACT:
A computer system has first and second random access memory (RAM) modules for storing digital information, and first and second system controllers coupled to the first and second RAM modules, respectively. The first system controller has a first address decoder that allocates to the first RAM module a first set of addresses. The second system controller has a second address decoder that allocates to the second RAM module a second set of addresses. By employing two system controllers to control two RAM modules, a computer system can execute two memory transactions simultaneously and can eliminate or reduce the number of memory access delays incurred. The computer system can allocate addresses according to various interleaving schemes, such as page interleaving, cache line interleaving and word interleaving for different memory segments. A configuration register can be employed to allow programming to select which of the interleaving schemes to employ.

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Shanley and Anderson, "ISA System Architecture," Addison-Wesley Publishing Co., 3.sup.rd Ed., pp. 235-272, Feb. 1995.

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