Thread switch on blocked load or store using instruction thread

Thread-local synchronization construct cache

Time based mechanism for cached speculative data deallocation

Time-stamp and hash-based file modification monitor with multi-u

Timing consistent dynamic compare with force miss circuit

TLB operation based on task-ID

TLB operations based on shared bit

Token based cache-coherence protocol

Trace based deallocation of entries in a versioning cache...

Trace based instruction caching

Trace cache filtering

Trace cache for efficient self-modifying code processing

Trace victim cache

Tracing instruction flow in an integrated processor

Tracing instruction flow in an integrated processor

Tracking temporal use associated with cache evictions

Transaction activation processor for controlling memory transact

Transaction manager and cache for processing agent

Transaction references for requests in a multi-processor...

Transfer of cache lines on-chip between processing cores in...