Thread switch on blocked load or store using instruction thread

Details Thread switch on blocked load or store using instruction thread Thread switch on blocked load or store using instruction thread

1996-07-01

1999-08-03

Lee, Thomas C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711152, 711122, 395677, G06F 1516, G06F 938

Patent

active

059336277

ABSTRACT:
A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

REFERENCES:
patent: 5361337 (1994-11-01), Okin
patent: 5535361 (1996-07-01), Hirata et al.
patent: 5553305 (1996-09-01), Gregor et al.
patent: 5574939 (1996-11-01), Keckler et al.
Eickemeyer et al. (Evaluation of multithreaded uniprocessors for commercial application environments) pp. 203-212, May 1996.
Kawano et al. (Fine-grain multi-thread processor architecture for massively parallel processing) pp. 308-317, May 1995.

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