Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-08-21
2007-08-21
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S135000, C711S136000, C711S125000
Reexamination Certificate
active
09764810
ABSTRACT:
A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number of accesses to the trace.
REFERENCES:
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5446876 (1995-08-01), Levine et al.
patent: 5623627 (1997-04-01), Witt
patent: 5737565 (1998-04-01), Mayfield
patent: 5862371 (1999-01-01), Levine et al.
patent: 5944815 (1999-08-01), Witt
patent: 5999721 (1999-12-01), Colglazier
patent: 6009270 (1999-12-01), Mann
patent: 6018763 (2000-01-01), Hughes et al.
patent: 6018786 (2000-01-01), Krick et al.
patent: 6052700 (2000-04-01), Eckard et al.
patent: 6076144 (2000-06-01), Peled et al.
patent: 6167536 (2000-12-01), Mann
patent: 6170038 (2001-01-01), Krick et al.
patent: 6185669 (2001-02-01), Hsu et al.
patent: 6202126 (2001-03-01), Van Doren et al.
patent: 6205545 (2001-03-01), Shah et al.
patent: 6216206 (2001-04-01), Peled et al.
patent: 6237065 (2001-05-01), Banerjia et al.
patent: 6272598 (2001-08-01), Arlitt et al.
patent: 6282616 (2001-08-01), Yoshida et al.
patent: 6295644 (2001-09-01), Hsu et al.
patent: 6332179 (2001-12-01), Okpisz et al.
patent: 6332189 (2001-12-01), Baweja et al.
patent: 6351844 (2002-02-01), Bala
patent: 6393522 (2002-05-01), Campbell
patent: 6397296 (2002-05-01), Werner
patent: 6397302 (2002-05-01), Razdan et al.
patent: 6418530 (2002-07-01), Hsu et al.
patent: 6425057 (2002-07-01), Cherkasova et al.
patent: 6453411 (2002-09-01), Hsu et al.
patent: 6542966 (2003-04-01), Crawford et al.
patent: 6604060 (2003-08-01), Ryan et al.
patent: 6775695 (2004-08-01), Sarukkai
patent: 2001/0032307 (2001-10-01), Rohlman et al.
patent: 2002/0066081 (2002-05-01), Duesterwald et al.
Jim Handy, “The Cache Memory Book”, 1993, Academic Press, pp. 37-107.
Sato, T., Evaluating trace cache on moderate-scale processors, Computers and Digital Techniques, IEE Proceedings-, vol. 147 Issue: 6, Nov. 2000, pp. 369-374.
Rakvic, R.; Black, B.; Shen, J.P., Completion time multiple branch prediction for enhancing trace cache performance, Computer Architecture, 2000. Proceedings of the 27th International Symposium on , 2000, pp. 47-58.
Patel, S.J.; Friendly, D.H.; Patt, Y.N., Evaluation of design options for the trace cache fetch mechanism, Computers, IEEE Transactions on , vol. 48 Issue:2 , Feb. 1999, pp. 193-204.
Rotenberg, E.; Bennett, S.; Smith, J.E., A trace cache microarchitecture and evaluation, Computers, IEEE Transactions on , vol. 48 Issue: 2 , Feb. 1999, pp. 111-120.
Howard, D.L.; Lipasti, M.H., The effect of program optimization on trace cache efficiency, Parallel Architectures and Compilation Techniques, 1999. Proceedings. 1999 International Conference on, 1999, pp. 256-261.
Black, B.; Rychlik, B.; Shen, J.P., The block-based trace cache, Computer Architecture, 1999. Proceedings of the 26th International Symposium on , 1999, pp. 196-207.
Patel, S.J.; Evers, M.; Patt, Y.N., Improving trace cache effectiveness with branch promotion and trace packing, Computer Architecture, 1998. Proceedings. The 25th Annual International Symposim on, 1998, pp. 262-271.
Friendly, D.H.; Patel, S.J.; Patt, Y.N., Putting the fill unit to work: dynamic optimizations for trace cache microprocessors, Microarchitecture, 1998. MICRO-31. Proceedings. 31st Annual ACM/IEEE nternational Symposium on , 1998, pp. 173-181.
Friendly, D.H.; Sanjay Jeram Patel; Patt, Y.N., Alternative fetch and issue policies for the trace cache fetch mechanism, Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on , 1997, pp. 24-33.
Rotenberg, E.; Bennett, S.; Smith, J.E., Trace cache: a low latency approach to high bandwidth instruction fetching, Microarchitecture, 1996. MICRO-29. Proceedings of the 29th Annual IEEE/ACM International Symposium on , 1996, pp. 24-34.
“The cache Memory Book”, Jim Handy, Academic Press, 1993, pp. 37-93.
Mendelson Abraham
Ronen Ronny
Rosner Roni
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Hong
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