Transaction references for requests in a multi-processor...

Details Transaction references for requests in a multi-processor... Transaction references for requests in a multi-processor...

2004-01-15

2010-12-21

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S150000, C711SE12032

Reexamination Certificate

active

07856534

ABSTRACT:
One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.

REFERENCES:
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5657472 (1997-08-01), Van Loo et al.
patent: 5721855 (1998-02-01), Hinton et al.
patent: 5802577 (1998-09-01), Bhat et al.
patent: 5829040 (1998-10-01), Son
patent: 5875467 (1999-02-01), Merchant
patent: 5875472 (1999-02-01), Bauman et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6081874 (2000-06-01), Carpenter et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6108737 (2000-08-01), Sharma et al.
patent: 6122714 (2000-09-01), VanDoren et al.
patent: 6279084 (2001-08-01), Van Doren et al.
patent: 6345342 (2002-02-01), Arimilli et al.
patent: 6457100 (2002-09-01), Ignatowski et al.
patent: 6490661 (2002-12-01), Keller et al.
patent: 6631401 (2003-10-01), Keller et al.
patent: 2001/0034815 (2001-10-01), Dugan et al.
patent: 2002/0009095 (2002-01-01), Van Doren et al.
patent: 2002/0073071 (2002-06-01), Pong et al.
patent: 2002/0124143 (2002-09-01), Barroso et al.
patent: 2002/0144063 (2002-10-01), Peir et al.
patent: 2002/0184453 (2002-12-01), Hughes et al.
patent: 2002/0194290 (2002-12-01), Steely, Jr. et al.
patent: 2003/0018739 (2003-01-01), Cypher et al.
patent: 2003/0076831 (2003-04-01), Van Doren et al.
patent: 2003/0140200 (2003-07-01), Jamil et al.
patent: 2003/0145136 (2003-07-01), Tierney et al.
patent: 2003/0195939 (2003-10-01), Edirisooriya et al.
patent: 2003/0200397 (2003-10-01), McAllister et al.
Rajeev , Joshi, et al., “Checking Cache-Coherence Protocols with TLA+”, Kluwer Academic Publishers, 2003, pp. 1-8.
Martin, Milo M.K., et al., “Token Coheence: Decoupling Performance and Correctness”, ISCA-30, pp. 1-12, Jun. 9-11, 2003.
Acacio, Manuel E., et al., “Owner Prediction for Accelerating Cache-to-Cache Transfer Misses in a cc-NUMA Architecture”, IEEE 2002.
Gharachorloo, Kourosh, et al., “Architecture and Design of AlphaServer GS320”, Western Research Laboratory.
Gharachorloo, Kourosh, et al., “Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors”, Computer Systems Laboratory, pp. 1-14.

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