Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-04-12
2011-04-12
Tran, Denise (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S136000, C711SE12020
Reexamination Certificate
active
07925834
ABSTRACT:
A method and apparatus for tracking temporal use associated with cache evictions to reduce allocations in a victim cache is disclosed. Access data for a number of sets of instructions in an instruction cache is tracked at least until the data for one or more of the sets reach a predetermined threshold condition. Determinations whether to allocate entry storage in the victim cache may be made responsive in part to the access data for sets reaching the predetermined threshold condition. A micro-operation can be inserted into the execution pipeline in part to synchronize the access data for all the sets. Upon retirement of the micro-operation from the execution pipeline, access data for the sets can be synchronized and/or any previously allocated entry storage in the victim cache can be invalidated.
REFERENCES:
patent: 2006/0230235 (2006-10-01), O'Connor et al.
patent: 2008/0065865 (2008-03-01), Kim et al.
Baliga Harikrishna
Ekpanyapong Mongkol
Kim Ilhyun
Smith Peter J.
Intel Corporation
Tran Denise
Trop Pruner & Hu P.C.
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