Transfer of cache lines on-chip between processing cores in...

Details Transfer of cache lines on-chip between processing cores in... Transfer of cache lines on-chip between processing cores in...

2006-10-10

2006-10-10

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S120000, C711S124000, C711S146000

Reexamination Certificate

active

07120755

ABSTRACT:
Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.

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