Structure for handling data access
Structure for handling data requests
Structure for power-efficient cache memory
Structure for shared cache eviction
Subsettable top level cache
Super-coherent data mechanisms for shared caches in a...
Super-coherent multiprocessor system bus protocols
Superscalar microprocessor employing away prediction structure
Superscalar microprocessor including a cache configured to detec
Superscalar microprocessor including a decoded instruction cache
Superscalar microprocessor including a reorder buffer which dete
Superscalar processor employing a high performance write...
Supporting directory-based cache coherence in an...
Supporting speculative modification in a data cache
Supporting speculative modification in a data cache
Surface or underwater dive vehicle
Symmetric multiprocessing system with unified environment and di
Symmetric multiprocessor address bus protocol with...
Symmetric multiprocessor coherence mechanism
Symmetric multiprocessor systems with an independent...