Structure for shared cache eviction

Details Structure for shared cache eviction Structure for shared cache eviction

2008-05-01

2011-11-22

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711SE12052

Reexamination Certificate

active

08065487

ABSTRACT:
A design structure embodied in a machine readable storage medium for of designing, manufacturing, and/or testing for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores is provided. The design structure includes means for receiving from a processor core a request to load a cache line in the shared cache; means for determining whether the shared cache is full; means for determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and means for evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.

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Kim Hazelwood et al., “Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems,” Proceedings of the International Symposium on Code Generation and Optimization, 2004, IEEE Computer Society.

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