Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-03-08
1998-09-22
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711145, 711119, 711141, 711124, G06F 1200
Patent
active
058130330
ABSTRACT:
A microprocessor is provided including a pair of caches and a dependency checking structure for accesses between the pair of caches. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit. When accesses are performed from the execute stage, the dependency bits are checked to determine if a dependency exists with respect to an access performed from the decode stage. Corrective actions are performed based on analysis of the dependency bits. Correct results are maintained for the cases in which dependencies exist by effectively forcing the accesses to occur in program order.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama
patent: 5155832 (1992-10-01), Hunt
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5251306 (1993-10-01), Tran
patent: 5377336 (1994-12-01), Eickemeyer et al.
patent: 5404552 (1995-04-01), Ikenage
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5557763 (1996-09-01), Senter et al.
patent: 5584009 (1996-12-01), Garibay, Jr. et al.
patent: 5636353 (1997-06-01), Ikenaga et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?" PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," Byte, Jan. 1996, 4 pages.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Merkel Lawrence J.
Swann Tod R.
Tzeng Fred Fei
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