Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Utility Patent
1997-11-06
2001-01-02
Gossage, Glenn (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S169000, C710S052000, C712S023000
Utility Patent
active
06170040
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a processor having a high performance in a write cycle and, more particularly, to a processor capable of lessening a bottle neck caused systematically, by employing a write buffer and a state machine controlling the write buffer and diminishing write cycles.
DESCRIPTION OF THE PRIOR ART
There is generally caused in a conventional processor a bottle neck in a systematical performance thereof, since data is processed much more quickly in a processor than in a memory or a peripheral input/output apparatus. For settling such shortcomings, it has been employed to install a cache in a processor; that is, a curtailment of cycles for most cycles is actually realized through a processing via an internal cache in place of processing via an external memory.
All bus cycles are not, however, processed via the internal cache contained in the processor and it is not a fundamental solution in preventing a bus cycle from being processed externally. In spite of an internal installment of the cache therein, in case of an occurrence of a cache miss or in case of an inevitable necessity of an external cycle processing required for a cache data coherency algorithm, internal core units should wait until corresponding operations of the bus unit are finished in an external memory having a comparatively slow process speed or in a secondary cache, which brings about an overall performance drop of a system. In a microprocessor of a superscalar structure having a plurality of pipelines, specially, it is inevitable to need a system for settling such defect since its occurrence rate is higher than in a processor having a single pipeline structure.
For example, a complex instruction set computer (CISC) having complicated instruction words uses many more memory operands in comparison with a reduced instruction set computer (RISC), thus a processor having the CISC structure may function with a higher performance by decreasing the number of cycles in a memory access. An internal cache is employed for reducing such cycles and the processor may process an operation required in the internal cache when an address line desired therein is discovered.
A reading operation is generally available in reading data since its operation is not to change the data. However, a care needs to be taken in writing data since its operation is to change data of an address to be written. If a changed data is written in the internal cache and not written in an external memory, there exists old data in the external memory. If an outer another bus master tries to write data in the external memory and a line of its corresponding address exists at the internal cache, only the data at the memory is changed while the internal cache stores old data. Such problems caused between cache data and memory data in case of using the cache in a system having several numbers of bus masters need to be settled in the cache data coherency algorithm. For the cache coherency settlement, the microprocessors use several kinds of schemes and there is omitted a detailed description in the present invention since the invention is related specially to a write buffer.
In the processor, e.g., the Pentium™ microprocessor from Intel Corp., San Jose, Calif., a difference between the cache data and the memory data is settled through a use of a write once policy which is to process a external cycle, at one time, for an initial writing. In other words, despite an installment of the internal cache, a necessity of the external write cycle is required for the cache data coherency algorithm with the exterior data. Also, the write cycle is inevitable to be processed externally in case of an occurrence of the cache miss.
As above-mentioned, it is difficult to settle completely the bottle neck in the system performance, with only installment of the internal cache, in case of an inevitable external cycle process. That is, the internal core units need to wait until the bus unit is used for the external memory having a comparatively slow process speed or the secondary cache, which degrades an overall performance of the system.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the invention to provide a processor capable of lessening a bottle neck caused systematically, by employing a write buffer and a state machine controlling the write buffer and diminishing write cycles.
In accordance with the present invention, in reading data, external units should wait until a reading operation is finished since the data must be used subsequently. In writing the data, the external units do not need to wait until a writing operation is completely finished since the data is not used subsequently. Considering this aspect, in a case the bus cycle should be inevitably processed externally, a write buffer capable of allowing a subsequent operation to be done is employed in the present invention since the writing operation does not have a direct influence upon the subsequent operation. Especially in the superscalar structure, one write buffer is respectively provided with every each pipeline for the sake of a higher performance.
Accordingly, the internal core unit regards the writing in the write buffer instead of an actual process of a external write cycle, as a completion of a writing operation, then performs a next operation; when it also becomes a situation for using a CPU bus, data of the write cycle stored in the write buffer may be processed externally. The core unit regards such operation of the write buffer as a process of the external cycle and the write buffer is made up of several blocks storing information, e.g., a write address, data, a volume of the operand etc.
In a microprocessor of a superscalar structure having a datapath, a data cache and a bus unit, the microprocessor include a write buffer equipped in the bus unit and a write back buffer installed at the data cache. In this case, data of a burst write cycle is received through the write back buffer and data of a single write cycle is received through a path from the datapath to the write buffer of the bus unit.
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Kim Han Heung
Lee Suk Joong
Gossage Glenn
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
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