Instruction cache, decoder circuit, basic block cache...
Instruction fetch on demand for uncacheable memory which avoids
Instruction prefetch caching for remote memory
Instruction processor write buffer emulation using embedded...
Instruction unit having a partitioned cache
Instruction-assisted cache management for efficient use of...
Instructions for test & set with selectively enabled...
Integrated bus bridge and memory controller that enables data st
Integrated cache and directory structure for multi-level caches
Integrated cache buffers
Integrated circuit and method for buffering to optimize...
Integrated circuit I/O using a high performance bus interface
Integrated circuit memory device supporting an N bit...
Integrated hierarchical memory overlay having invariant...
Integrated processing and L2 DRAM cache
Integrated processor/memory device with victim data cache
Integrated processor/memory device with victim data cache
Integrated purge store mechanism to flush L2/L3 cache...
Intelligent cache management mechanism via processor access...
Intelligent cache replacement mechanism with varying and...