Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-03-02
2001-03-27
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06209061
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method and apparatus for improving memory performance in a computer and, more particularly, to a method and apparatus for achieving more efficient processing performance through use of an overlay memory for storage of intermediate processing data.
BACKGROUND OF THE INVENTION
Manufacturers of microprocessors continue to improve their performance by increasing the clock speed of their components. In order to capitalize on these clock speed increases, the microprocessor must maintain an efficient operation of memory systems, including cache memories. Since the improvements in memory systems have not kept pace with improvements in microprocessor design, the penalties for cache misses have become a critical component in overall system design.
As is known to those skilled in the art, a cache memory is an area of buffer memory that is employed to store frequently used items and enables rapid accessibility thereto. A cache “hit” is when a particular item is found in the cache memory and a cache “miss” is when a particular item is not found in the cache memory and access must then be had to main memory to recover the required item. In the event of a cache miss, access to the main memory occurs via a relatively slow speed process which slows overall system operation. Further, when a write occurs to a cache line, the entire line is marked as “dirty”, indicating an inconsistent state with the corresponding data in main memory. Thereafter, the entire cache line needs to be posted to main memory to remove the cache line's dirty state, a further time consuming action.
To improve the accessibility of certain processing variables, current operating systems allocate regions of memory, on a temporary basis, for storage of such variables. These temporarily allocated regions are termed “stacks”. It has been determined that, with certain complex imaging applications, from 15% to 50% of external data memory accesses are made to such stack structures. Accordingly, memory performance can be improved if the operation of stack structures is optimized.
The prior art has attempted to enhance stack operation by providing small amounts of expensive, high speed/low latency memory where the stacks could be placed. This approach is relatively expensive and the designer needs to ensure that enough such high speed/low latency memory is available for system stack needs. If the system designer does not provide sufficient memory for stack purposes, late changes in the programs are required to compensate for the greater stack space need.
In general, designers are conservative in providing for stack space, in that such stack space is over-allocated so that it is never completely consumed. Thus, the designer is generally forced to provide an additional 10% of stack space over what is considered to be a worst case situation. Further, in such stack arrangements, it is often found that there is much activity near the base of the stack and little or no activity near the top of the stack.
As indicated above, when a write is made to a cache line, the associated cache memory controller marks the data as “dirty” in the accessed cache line. The data resident at that cache line is then posted to main memory, at some point in time, even if the relevant portion of the cache is associated with a stack. Since the portion of the cache memory associated with a stack receives frequent “hits”, that portion of the cache requires frequent cache management actions, thus reducing the system's performance efficiency.
A further approach to improving stack memory operation is to split the stack into pieces, one piece that resides in high speed memory and another piece which exists in lower speed memory (e.g., main memory). This arrangement requires that the software/firmware that manages the system stack resources must check for the transition point between the different physical components of the logical stacks. Such a “stack sentinel” requires relatively small size code, but is executed hundreds of thousands of times for tasks of moderate difficulty. Thus, while this approach helps address the cost issues of providing high performance stack memory, it requires some performance degradation to manage the stack activity. Further, it requires some external access to main memory, resulting in a degree of delay in microprocessor operations.
Accordingly, it is an object of this invention to provide an improved method and apparatus for management of memory usage in a microprocessor.
SUMMARY OF THE INVENTION
It has been determined that considerable data which is written to stacks is of the type that does not require long term retention (i.e., it is only required to be valid for the duration of a procedure or function which created it). Accordingly, when a stack is employed to handle such data (and other similar data), invalidation and writes to main memory that ordinarily accompany accesses of such data (when the stack is held in a cache memory) can be avoided. The invention therefore improves memory performance by providing an overlay memory, to which is assigned a set of main memory addresses that are utilized for stack operations. When data is either read or written from/to the overlay memory, there is no further communication “downstream” to either a cache memory or main memory. In other words, the overlay memory is used for short term storage and accesses to the overlay memory are invisible to other memory elements of the system. There is thus no need to invalidate any data or to write such data to main memory. As a result, substantially improved memory operations result.
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Matthews Randy J.
Nelson Marvin D.
Ellis Kevin L.
Hewlett-Packard Co.
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