Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-06-19
2007-06-19
Tran, Denise (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C713S400000
Reexamination Certificate
active
10045591
ABSTRACT:
A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.
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Brandt et al., “The benchmarker's Guide for CRAY SV1 Systems”, Jul. 20, 2000, pp. 1-39.
Baird Robert J.
Kohn James R.
Cray Inc.
Schwegman, Lundberg, Woessner and Kluth P.A.
Tran Denise
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