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Cache coherency protocol in which a load instruction hint...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol including a hovering (H) state...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol including an HR state

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol including generic transient states

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol including generic transient states

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol permitting sharing of a locked data...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol with ambiguous state for posted...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol with efficient write-through aliasing

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol with independent implementation of opti

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol with selectively implemented tagged...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol with tagged intervention of...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocol with tagged state for modified values

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocols with global and local posted...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocols with posted operations

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency protocols with posted operations and tagged cohe

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency test system and methodology for testing cache op

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherency where multiple processors may access the same da

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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CACHE COHERENT CONTROL SYSTEM FOR NETWORK NODES ALLOWS CPU...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherent network adapter for scalable shared memory proces

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Cache coherent network adapter for scalable shared memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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