Cache coherency protocol with efficient write-through aliasing

Details Cache coherency protocol with efficient write-through aliasing Cache coherency protocol with efficient write-through aliasing

1997-12-17

2000-02-01

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711138, 711142, 711144, 711145, 711146, G06F 1208

Patent

active

060214686

ABSTRACT:
A method of maintaining cache coherency in a multi-processor computer system, which avoids unnecessary writing of values to lower level caches in response to write-through store operations. When a write-through store operation is executed by a processing unit, the modified value is stored in its first level (L1) cache, without storing the value in a second level (L2) cache (or other lower level caches), and a new coherency state is assigned to the lower level cache to indicate that the value is held in a shared state in the first level cache but is undefined in the lower level cache. When the value is written to system memory from a store queue, the lower level cache switches to the new coherency state upon snooping the broadcast from the store queue. This approach has the added benefit of avoiding the prior art read-modify-write process that is used to update the lower level cache.

REFERENCES:
patent: 5671391 (1997-09-01), Knotts
patent: 5787478 (1998-07-01), Hicks et al.

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