Cache coherency protocol including generic transient states

Details Cache coherency protocol including generic transient states Cache coherency protocol including generic transient states

2004-04-26

2008-03-25

Sparks, Donald A. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C707S793000

Reexamination Certificate

active

07350032

ABSTRACT:
In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.

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