Cache coherency protocol including an HR state

Details Cache coherency protocol including an HR state Cache coherency protocol including an HR state

1998-02-17

2001-08-14

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S142000, C711S144000, C711S145000, C711S130000

Reexamination Certificate

active

06275908

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to a method and system for maintaining cache coherency in a multiprocessor data processing system. Still more particularly, the present invention relates to an improved cache coherency protocol for a multiprocessor data processing system that includes at least one state, which although indicative of invalid data, can transition to another state from which data can be sourced by intervention.
2. Description of the Related Art
In a conventional symmetric multiprocessor (SMP) data processing system, all of the processors are generally identical, that is, the processors all utilize common instruction sets and communication protocols, have similar hardware architectures, and are generally provided with similar memory hierarchies. For example, a conventional SMP data processing system may comprise a system memory, a plurality of processing elements that each include a processor and one or more levels of cache memory, and a system bus coupling the processing elements to each other and to the system memory. To obtain valid execution results in an SMP data processing system, it is important to maintain a coherent memory hierarchy, that is, to provide a single view of the contents of memory to all of the processors.
A coherent memory hierarchy is maintained through the use of a selected memory coherency protocol, such as the MESI protocol. In the MESI protocol, an indication of a coherency state is stored in association with each coherency granule (e.g., cache line or sector) of at least all upper level (cache) memories. Each coherency granule can have one of four states, modified (M), exclusive (E), shared (S), or invalid (I), which is indicated by two bits in the cache directory. The modified state indicates that a coherency granule is valid only in the cache storing the modified coherency granule and that the value of the modified coherency granule has not been written to system memory. When a coherency granule is indicated as exclusive, the coherency granule is resident in, of all caches at that level of the memory hierarchy, only the cache having the coherency granule in the exclusive state. The data in the exclusive state is consistent with system memory, however. If a coherency granule is marked as shared in a cache directory, the coherency granule is resident in the associated cache and in at least one other cache at the same level of the memory hierarchy, all of the copies of the coherency granule being consistent with system memory. Finally, the invalid state indicates that the data and address tag associated with a coherency granule are both invalid.
The state to which each coherency granule (e.g., cache line) is set is dependent upon both a previous state of the cache line and the type of memory access sought by a requesting processor. Accordingly, maintaining memory coherency in the multiprocessor data processing system requires that the processors communicate messages across the system bus indicating their intention to read or write memory locations. For example, when a processor desires to write data to a memory location, the processor must first inform all other processing elements of its intention to write data to the memory location and receive permission from all other processing elements to carry out the write operation. The permission messages received by the requesting processor indicate that all other cached copies of the contents of the memory location have been invalidated, thereby guaranteeing that the other processors will not access stale local data. This exchange of messages is known as cross-invalidation (XI).
The present invention includes a recognition that while cross-invalidation of cache entries serves to maintain memory coherency in a SMP data processing system, the invalidation of cache entries by remote processors adversely affects data processing system performance by decreasing hit ratios in local caches. Thus, even if equipped with large local caches, a processing element can incur long access latencies when retrieving data that were once resident in a local cache from either a remote cache in another processing element or from system memory. As should thus be apparent, it would be desirable to provide a method and system for maintaining memory coherency in a SMP data processing system that reduces the performance penalty incurred as a result of the cross-invalidation of cache entries.
The present invention also includes a recognition that the conventional MESI protocol does not support efficient retrieval of data stored in remote caches. Although some known multiprocessor data processing systems support so-called modified intervention, which permits a remote cache storing data in the modified state to supply the modified data in response to a read request, the MESI protocol does not allocate responsibility for sourcing data to another processing element when the requested data is in the shared state. Thus, although requested data may be stored in multiple remote caches at a relatively low access latency, in conventional multiprocessor data processing systems shared data must always be retrieved from system memory. It would therefore be desirable to provide an improved cache coherency protocol that supports shared intervention.
In conventional multiprocessor data processing systems that support modified intervention, modified data is written back to system memory each time the modified data is sourced to another cache across the shared bus. The present invention includes a recognition that while this procedure does maintain coherency between system memory and cache memory, it consumes a portion of the limited bandwidth of the system memory in order to perform a write operation that may be unnecessary. For example, if a modified cache line is sourced by a first cache to a second cache in response to a read request, the data in the second cache is likely to be modified again, thus requiring another write to system memory. If no other request for the cache line is issued between the time of the second cache's read request and subsequent modification of the cache line, then the write to system memory concomitant with modified intervention by the first cache is superfluous.
One possible method for reducing unnecessary write backs to system memory would be to mark data as invalid in the sourcing cache and as modified in the requesting cache, even if the requesting cache only made a read request. In this manner, the requested data need not be written back to system memory in conjunction with modified intervention. However, this method of maintaining cache coherency does not permit sharing of modified data between processors and would create additional bus traffic as data is passed between caches. It would therefore be desirable to provide an improved cache coherency protocol that supports efficient writeback of data to system memory while permitting modified data to be shared between caches.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved method and system for maintaining cache coherency in a multiprocessor data processing system.
It is yet another object of the present invention to provide a cache coherency protocol for a multiprocessor data processing system that includes at least one state, which although indicative of invalid data, can transition to another state from which data can be sourced by intervention.
The foregoing objects are achieved as is now described. A data processing system is provided that includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. In accordance with the method of the present invention, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is

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