Verifying an IC layout in individual regions and combining...
Verifying an IC layout in individual regions and combining...
Verifying decoupling capacitance using a maximum flow...
Verifying hardware in its software context and vice-versa
Verifying logic synthesizers
Verifying on-chip decoupling capacitance
Verifying one or more properties of a design using SAT-based...
Verifying proximity of ground metal to signal traces in an...
Verifying proximity of ground vias to signal vias in an...
Verilog to vital translator
Versatile multiplexer-structures in programmable logic using...
Versatile multiplexer-structures in programmable logic using...
Vertex based layout pattern (VEP): a method and apparatus...
Via density change to improve wafer surface planarity
Via enclosure rule check in a multi-wide object class design...
Via redundancy based on subnet timing information, target...
Via structure to improve routing of wires within an...
Via/BSM pattern optimization to reduce DC gradients and pin...
Video processing architecture definition by function graph...
Virtual component having a detachable...