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Reconfiguring a RAM to a ROM using layers of metallization

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Recovery path designing circuit, method and program thereof

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Recursive partitioning placement method and apparatus

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Redistribution metal for output driver slew rate control

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Redistribution metal for output driver slew rate control

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Redistribution of current demand and reduction of power and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reduced architecture processing paths

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reduced pessimism clock gating tests for a timing analysis tool

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing cell library development cycle time

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing clock skew in clock gating circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing clock skew in clock gating circuits

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing coupling between wires of an electronic circuit

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Reducing critical cycle delay in an integrated circuit...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
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Reducing datapath widths by rebalancing data flow topology

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing datapath widths responsively to upper bound on...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing design execution run time bit stream size for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing equivalence checking complexity using inverse function

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing I/O supply noise with digital control

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Reducing susceptibility of circuit designs to single event...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
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Reducing time to design integrated circuits including...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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