Reduced architecture processing paths

Details Reduced architecture processing paths Reduced architecture processing paths

2006-11-14

2006-11-14

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07137082

ABSTRACT:
A basic Boolean circuit is a transistor circuit commonly used in industry to produce the logic of a particular Boolean gate. A sequence of standard Boolean circuits disposed along the processing path of an integrated circuit define a predetermined truth table representing the relationship of inputs and outputs of the processing path. A reduced-transistor circuit is generated that is defined by the same truth table as the sequence of standard Boolean logic circuits, but is not definable by a sequence of standard Boolean logic circuits. A processing path of an integrated circuit is programmed with the reduced-transistor circuit instead of the sequence of standard Boolean circuits, thereby reducing the time delay of the processing path and the power consumed by the circuit. The reduced-transistor circuit may be generated in response to receiving a programming instruction defining a sequence of Boolean gates. Alternatively, the reduced-transistor circuit may be selected from a pre-established library storing a plurality of Boolean sequences correlated to a respective plurality of complimentary reduced-transistor circuits.

REFERENCES:
patent: 5243538 (1993-09-01), Okuzawa et al.
patent: 5345393 (1994-09-01), Ueda
patent: 5416719 (1995-05-01), Pribetich
patent: 5519627 (1996-05-01), Mahmood et al.
patent: 5521836 (1996-05-01), Hartoog et al.
patent: 5586046 (1996-12-01), Feldbaumer et al.
patent: 5586047 (1996-12-01), Imahashi
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5748497 (1998-05-01), Scott et al.
patent: 5812417 (1998-09-01), Young
patent: 5838583 (1998-11-01), Varadarajan et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5850349 (1998-12-01), Hirai et al.
patent: 6026222 (2000-02-01), Gupta et al.
patent: 6056784 (2000-05-01), Stanion
patent: 6086629 (2000-07-01), McGettigan et al.
patent: 6145117 (2000-11-01), Eng
patent: 6163876 (2000-12-01), Ashar et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6430734 (2002-08-01), Zahar
patent: 6434734 (2002-08-01), Zahar
patent: 6438736 (2002-08-01), Zahar
patent: 6520063 (2003-02-01), Schluter
patent: 6530063 (2003-03-01), Andreev et al.
patent: 6544806 (2003-04-01), Snider
patent: 6584605 (2003-06-01), Zahar
patent: 6587990 (2003-07-01), Andreev et al.
patent: 6606737 (2003-08-01), Zahar
patent: 6687892 (2004-02-01), Zahar
patent: 6829753 (2004-12-01), Lee et al.
P. Ienne et al., “Practical Experiences with Standard-Cell Based Datapath Design Tools—Do We Really Need Regular Layouts?”, 24.4, Jun. 1998, pp. 396-401.
R. Gordon et al., “An N-Bus Datapath Compiler for IC Design”, Silicon Compiler Systems Corp., 1989 IEEE, pp. 23.3.1-23.3.4.

Affiliated with

Also associated with

Rating

Reduced architecture processing paths does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduced architecture processing paths, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced architecture processing paths will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3645486