Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-18
2007-09-18
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10946274
ABSTRACT:
The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect over each cell, wherein the first metal layer comprises local core cell nodes and the second metal layer comprises power/ground. The RAM is also fabricated with metal junction points on the first metal layer in at least a portion of the intersections. Thereafter, the RAM is reconfigured to a ROM by forming vias between the intersections of the first and second metal layers over the junction points to connect the first metal layer to the second metal layer.
REFERENCES:
patent: 5378906 (1995-01-01), Lee
patent: 5995409 (1999-11-01), Holland
patent: 6304950 (2001-10-01), Inoue et al.
patent: 2002/0088996 (2002-07-01), Yoo et al.
Agrawal Ghasi
Faber Allen
Lin Sun James
LSI Corporation
Strategic Patent Group P.C.
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