Reduced pessimism clock gating tests for a timing analysis tool

Details Reduced pessimism clock gating tests for a timing analysis tool Reduced pessimism clock gating tests for a timing analysis tool

2001-07-05

2004-04-06

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06718523

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to timing analysis tools. More particularly, the present invention relates to an improved method and system for the calculation of quantities to perform clock gating tests at gating devices during an integrated circuit design.
2. Description of the Related Art
Integrated circuit (IC) manufacturers have continuously sought to build smaller and more efficient integrated circuit chips that contain an increasing number of devices. Because the designing of IC chips is so complex, a programmed data processor is essential. The most common method of designing logic circuits for placement on IC chips is done with the use of computer systems and software that use computer-aided design (CAD) tools. Particular components that allow for an efficient design, checking and testing of very large scale integrated circuits (VLSI) are referred to as logic synthesis and physical design tools.
A logic synthesis tool takes as input a functional description of a logic circuit, typically written in a language such as VHDL, and then converts it into a technology level description. The circuits in this technology level description are then placed and the wires interconnecting them are routed by physical design tools, producing a set layout level representation that a chip foundry can use to actually build the chip. The output of the logic synthesis tool is referred to as a net list, which is actually a list of cells from a technology library and the necessary interconnections between the cells. The output of the physical design tools includes a “placement” (the assignment to each circuit in the net list of a physical location on the chip), and a “routing” (the assignment to each net in the net list a set of wire segments which implement the interconnections defined by the net), collectively referred to as the physical layout of the chip. Thus, the output of the electronic design automation system may be regarded as a template for the fabrication of the physical embodiment of the integrated circuit.
While generating the netlist and physical layout of the IC, these CAD tools must meet the timing constraints that are specified as part of the design. Timing tools, such as IBM's “EinsTimer” tool system, provide timing analysis of circuit net lists and layouts by working in conjunction with the synthesis and physical design tools. Logical and physical changes, based on this analysis, can then be implemented to achieve the desired timing constraints.
Static timing tools are used to ensure that a design implementation (net list and layout) meet imposed timing requirements. Timing correctness could be verified using delay simulation, or dynamic timing analysis, instead, in which specific waveforms are applied to the inputs of the design and resulting waveforms are produced at all points in the design. Such methods are more accurate than static timing analysis, and because of this the delays, tests, and propagations computed by static timing analysis must generally be somewhat pessimistic, meaning that they require signals to arrive earlier (through larger setup test values) or to be held longer (through larger hold test values) than might actually be necessary for correct design operation. But complete verification through simulation requires that all possible sets of input waveforms be simulated, and the number of such sets grows exponentially with the number of design inputs, making it impossible in practice to completely verify a design. The goal of a static timing analysis method is to avoid optimism (i.e., saying that a design will operate correctly when there is some input pattern whose simulation will indicate a failure), while minimizing pessimism (i.e., requiring a signal to become stable earlier or remain stable later than would be required by the simulation of any possible input pattern. Thus one way to determine the correct setup or hold test between a pair of input signals to a gate is to simulate transitions on the input signals with a variety of different spacings (differences in arrival times), and find the minimum spacing which causes the gate to have the required output. This will be the criterion against which the invention described below is measured. In particular, a designer is often concerned with a clock signal of a synchronous digital design of an IC, which synchronizes the storage of data into storage elements such as latches or flip-flops. The data held in particular storage elements is not always required during every clock cycle, and clock gating signals can be used to turn off the clock signal to such portions of the design during selected clock cycles. This can be done for functional reasons and/or to reduce power consumption, since energy that is proportional to the capacitance of the clock net is required to cause clock transitions on the clock net. Gating the clock reduces the total capacitance being switched in any given cycle. As an example, an AND gate
140
used for clock gating is shown in
FIG. 1
along with idealized clock and gate signal waveforms, which are shown in FIG.
2
. In
FIG. 1
, the AND gate
140
outputs
120
a high signal only when the clock
100
and gate
110
signals are also at a high state. Therefore, the output
120
would have a high signal only when both the gate
110
and clock signal
100
are high during time
200
. Conversely, the output
120
would be low during the time
201
when only the clock signal was high. In this example, the gate signal
110
prevents the clock signal
100
from being output
120
during time
201
. This is commonly referred to as “clock gating”.
When clock gating is performed, it is important that the gate signal be stable during the portion of the clock cycle during which the clock is not to control the circuit in question. Thus, an AND gate disables pulses of an active-high clock, while an OR-gate disables pulses of an active-low clock. In other words, the clock gate is required to enable the entire clock pulse to pass through, or to block the entire clock pulse. If the timing of the gate signal is off, clock “clipping” (shortening of an intended clock pulse) and “glitching” (occurrence of a portion of an unintended clock pulse) can occur, as shown in FIG.
3
. More specifically, because the gate the signal
110
is shifted later in time in
FIG. 3
when compared to
FIG. 2
, the first clock signal
200
is shortened because the beginning portion is “clipped”. To the contrary, the clock signal
201
which should not have been output (should have been non-controlling) is inadvertently output to as a “glitch”.
This requirement on the clock gate signal is ensured through static timing analysis, in which tests are imposed between the clock and gate signals. In particular, a setup test is imposed requiring that the gate signal be stable before the clock transitions to the non-controlling state, and a hold test is imposed requiring that the gate signal be held stable until after the clock transitions to the controlling state. These tests can be performed at the inputs of the clock gate, but because the delays from the clock and gate input of the gating circuit may differ, this may not ensure proper operation. As an example, consider an AND gate, as shown in
FIG. 4
, wherein the delay from the gate input to the output (delta-g)
141
is larger than that from the clock input to the output (delta-c)
142
, as shown in FIG.
5
. Here, even though the input gate signal
110
arrives to disable the clock
100
before the clock input arrives, the delay difference within the AND circuit
140
causes a glitch to occur on the output. In other words, a glitch
500
would occur on the output
120
because the clock signal
100
was so much faster than the gate signal
110
, that the high clock signal
100
would arrive at the clock output
120
before the gate signal
110
had an opportunity to prevent it.
During the IC design, CAD tools are used that deal with timing constraints present throughout the circuitry. These tools provide t

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