Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-01-10
2004-12-21
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06834381
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to integrated circuit devices, and more particularly to a method for using redistribution metal to control the slew rate of output drivers.
BACKGROUND OF THE INVENTION
As integrated circuit devices become increasingly faster and more complex, the performance achievable in an integrated circuit system can be limited by the interconnections between such devices with one another and with other components on a circuit board. Whereas integrated circuit devices once had only a few interconnects, often hundreds of interconnects are now required in more complex devices. Forming hundreds of interconnects between a chip and circuit board, however, can be difficult since chips are typically fabricated with significantly finer resolution than that of circuit boards. Thus, to connect a fine resolution chip to a circuit board, often some form of packaging is required to route signals between the chip and the circuit board.
The resolution of a component such as a chip or circuit board is often represented in terms of “pitch”, which is the minimum distance between interconnects on a component. For example, chips may have off-chip interconnects separated by 200 microns or less, while a typical circuit board may only be capable of utilizing interconnects separated by 800 to 1000 microns or more. To provide the necessary interface, a chip package is typically used that has a substrate with one side having interconnects disposed at a corresponding pitch for the chip, and with the other side having interconnects disposed at a corresponding pitch for the circuit board. Conductive traces, herein referred to as “redistribution metal”, disposed within one or more layers in the package substrate then route the signals between the chip and the circuit board, using vias and/or through holes to route signals between multiple layers.
System performance is often limited by noise on signals transmitted between between a chip package and a circuit board. One predominant form of noise results from parasitic capacitance, inductance, and resistance due to the signal routing between the signal pad on the integrated circuit die and the circuit board trace.
For a more complete understanding of the invention,
FIG. 1
illustrates a circuit model diagram of a conventional output buffer
10
of an integrated circuit. Output driver
10
generally includes a pullup transistor
12
(such as p-channel field effect transistor (PFET) P
1
) and a pulldown transistor
14
(such as n-channel field effect transistor (NFET) N
1
). Output driver
10
also generally includes a predriver circuit
6
which generates a pullup signal PULLUP to control the pullup transistor
12
and a pulldown signal PULLDOWN to control the pulldown transistor
14
. Predriver circuit
6
determines the states of pullup signal PULLUP and pulldown signal PULLDOWN based on the state of received data signal DATA, and typically also on the state of an output enable signal OE. Output enable signal OE is used to place the driver
10
into a high-impedance state whereby the driver
10
does not actively drive the pad
8
. When the output driver
10
is enabled to actively drive the pad
8
, the output signal OUT to be driven onto the pad
8
is derived from the data signal DATA, and is characterized by a driver output impedance Z
D
.
When the pad
8
is to be driven to the high voltage level V
DD
, the predriver circuit
6
asserts (negative true) the signal PULLUP, thereby turning on transistor
12
and pulling the pad
8
to V
DD
. Conversely, when the pad
8
is to be driven to the low voltage level V
SS
, the predriver circuit
6
asserts (positive true) the signal PULLDOWN, thereby turning on transistor
14
and pulling the pad
8
to V
SS
. When the output driver
10
is not actively driving the pad
8
, that is, when the output enable signal OE is not asserted, the predriver circuit
6
deasserts both the pullup signal PULLUP and the pulldown signal PULLDOWN, thereby turning off both transistors
12
and
14
and placing the pad
8
into a high-impedance state. Pullup signal PULLUP and pulldown signal PULLDOWN are never both simultaneously asserted.
Output buffer
10
is connected to an external transmission line
22
at output pad
8
. The transmission line
22
is characterized by a characteristic impedance Z
O
and capacitance C
O
which together define the RC time constant of the line
22
. As known in the art, the RC time constant of a transmission line affects the rate at which a signal OUT driven onto the line will change from one voltage rail to the other (i.e., V
DD
-to-V
SS
or V
SS
-to-V
DD
). The signal on the transmission line
22
is also affected by a characteristic inductance L
O
in series between the pad
8
and power supply V
DD
of the integrated circuit. The inductance L
O
results from the bond connection (e.g., wire bond, ball bond) between the pad
8
and transmission line
22
.
The characteristic impedance Z
O
, capacitance C
O
, and inductance L
O
, are often termed the “parasitics” of the line
22
because, as is known in the art, these “parasitics” can be problematic in terms of signal noise and other performance factors. For example, one predominant problem resulting from transmission line parasitics is known as “simultaneously switching output” (SSO) noise. SSO noise occurs when multiple signals in close proximity to one another switch at the same time. The switching activity causes a large current spike flowing through the power and ground connections, resulting in power and ground supply bounce. The magnitude of the SSO noise depends on the effective inductance of the power and/or ground connections and the size of the current transient flowing therethrough. Accordingly, the faster the switching speed, the higher the SSO noise.
Reflection noise may also occur when the switching frequency approaches the RC time constant of the transmission line. The fast rise and fall of the high-speed signals on the line causes transients on the power supplies and undesirable wave reflections causing overshoot and undershoot.
Crosstalk noise arises when signals on parallel transmission lines are located too close in proximity to one another. Switching signals on an active line couple to less active or “quiet” parallel lines. Thus, the faster the rise time of the signal, the greater the crosstalk noise
Another predominant problem that occurs with integrated circuit output drivers is known as “power supply droop”. Due to large off-chip loads, output driver transistors N
1
and P
2
must be sized to allow sufficient current flow to the pad to meet the output load requirements. When several I/O drivers are attached to any one power pad, the demands on the power supply from the output drivers can cause signal droop on the power bus. Signal droop is problematic because it decreases the maximum current flow through the pullup driver PFET P
2
and therefore decreases the speed at which the signal transitions to the high state. Thus, reflection noise is generated when the signal switching speed approaches the decreased rise time due to the power droop. Similar problems occur with the ground supply.
Because the magnitude of each of the above enumerated noise signals depends on the rise time of the signal, noise problems may be alleviated by slowing the “slew rate” (flattening out the transition edges) of the signals generated by the high speed output drivers of the chip.
Prior art methods of controlling the slew rate involve additional circuitry which attempts to control the switching speed of the driver itself. However, additional circuitry involves additional complexity, cost, and chip real estate. Accordingly, a need exists for an improved method for controlling the slew rate of integrated circuit signals with lower complexity, cost, and space.
SUMMARY OF THE INVENTION
The present invention is a technique for controlling the slew rate of integrated circuit output drivers by leveraging the parasitic capacitance of redistribution metal in the integrated circuit.
In accordance with th
Agilent Technolgies, Inc.
Garbowski Leigh M.
LandOfFree
Redistribution metal for output driver slew rate control does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Redistribution metal for output driver slew rate control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redistribution metal for output driver slew rate control will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3280569