Reducing clock skew in clock gating circuits

Details Reducing clock skew in clock gating circuits Reducing clock skew in clock gating circuits

2001-12-06

2003-11-04

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06643829

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to digital circuits. In particular, the invention relates to clock gating circuits.
2. Description of Related Art
Synchronous sequential circuits rely on their clock signals for reliable operations. Clocked sequential elements such as flip-flops or registers transfer input data to output data at the transition of the clock signal. For proper loading, the input data have to meet the set-up and hold time requirements. Since these critical timing parameters are determined with respect to the clock signal, any clock skew or delay may cause timing violations, resulting in erroneous data loading. In addition, clock skews may also limit the operating frequency range, leading to degraded performance.
There are several sources that may cause clock skew in sequential circuits. One of the major sources is the use of gating circuitry to selectively enable or disable the clock signal. A typical gating circuitry may involve several levels of gating circuits, often in the form of AND or OR gates. These gates introduce undesirable delays and cause unpredictable timing problems. The problem is even more pronounced when circuits are prototyped in programmable devices such as field programmable logic arrays (FPGA's). In these programmable logic devices, the gated clock signals are typically routed on the general routing network due to the limited number of available dedicated clock routing networks. The general routing network usually introduces significant delays and unequal distribution of clocking signals to various sequential elements, causing clock skews at the clock inputs of the sequential elements.
One technique to reduce clock skew is to use delay elements at various points in the clock signal paths to compensate for the unequal delays. This technique increases amount of hardware and circuit complexity. In addition, the delay elements may have their own delay variations which may not compensate well.
Therefore, there is a need to have an efficient technique to reduce clock skews and clock delays in sequential circuits.


REFERENCES:
patent: 6301553 (2001-10-01), Burgun et al.

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