Reducing susceptibility of circuit designs to single event...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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Details

C716S106000, C716S111000, C716S116000, C716S117000, C716S136000

Reexamination Certificate

active

08065644

ABSTRACT:
A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility. The circuit design including the mitigated region can be output.

REFERENCES:
patent: 6986078 (2006-01-01), Rodbell et al.
patent: 7249010 (2007-07-01), Sundararajan et al.
patent: 2004/0187050 (2004-09-01), Baumann et al.
patent: 2004/0230935 (2004-11-01), Samudrala et al.
“Estimation of Single Event Upset Probability Impact of FPGA Designs”, by Prasanna Sundararajan, Cameron Patterson, Carl Carmichael, Scott McMillan, and Brandon Blodget, by Xilinx, @ Aug. 12, 2003.
“SEU Mitigation for Sram-Based FPGAs through Dynamic Partial Reconfiguration”, by Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio, GLSVLSI'07, Mar. 11-13, 2007, @2007 ACM.
“Designing Single Event Upset Mitigation Techniques for Large SRAM-based FPGA Devices”, Thesis proposal by Fernanda Gusmao de Lima, Feb. 11th, 2002.
Pratt, Brian et al., “Improving FPGA Design Robustness with Partial TMR,” 12thNASA Symposium on VLSI Design, Oct. 4-5, 2005, pp. 1-7, Coeur d'Alene, Idaho.

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