Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-24
2007-04-24
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10958316
ABSTRACT:
A novel method is presented for mapping a signal driver of an integrated circuit to one of a plurality of interconnect pads. The output impedance of the signal driver and desired slew rate for a signal generated by the signal driver is used to calculate a desired characteristic capacitance to provide a resulting characteristic time constant required to achieve the desired slew rate on a transmission line connected to receive the signal. The characteristic capacitance associated with each at least one possible interconnection path between the driver and pad is estimated, and one of the interconnection paths whose associated characteristic capacitance is substantially equal to the desired characteristic capacitance is selected, and the output driver is then mapped to the pad associated with the selected interconnection path.
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Avago Technologies General IP ( Singapore) Pte. Ltd.
Garbowski Leigh M.
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