Representing device layout using tree structure
Representing device layout using tree structure
Representing the behaviors of a packet processor
Representing the design of a sub-module in a hierarchical...
Reset control for systems using programmable logic
Reset manager
Resettable memory apparatuses and design
Resettable memory apparatuses and design
Resistance and capacitance estimation
Resistor circuit
Resolution of dynamic memory allocation/deallocation and...
Resolving LBIST timing violations
Resolving phase-shift conflicts in layouts using weighted...
Resolving phase-shift conflicts in layouts using weighted...
Resonance reduction arrangements
Resonant tree driven clock distribution grid
Resonant tree driven clock distribution grid
Resource activity aware system for determining a resource...
Resource estimation for design planning
Resource mapping of functional areas on an integrated circuit