Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-08
2007-05-08
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10872966
ABSTRACT:
An aspect of the present invention provides a design environment in which a floorplan of a semiconductor device is optimised by taking into account activation or access frequency information to and from resources. Since segmented bus architecture is also a good alternative approach for the power consumption of the network, the floorplanning approach for energy optimization of the communicating network is adapted for such architectures in embodiments of the present invention. The provided method comprises both architecture optimizations as well as physical design optimizations.
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Catthoor Francky
Guo Jin
Miranda Miguel
Papanikolaou Antonis
Wang Hua
Garbowski Leigh M.
Interuniversitar Microelektronica Centrum (IMEC)
Knobbe Martens Olson & Bear LLP
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