Resolving LBIST timing violations

Details Resolving LBIST timing violations Resolving LBIST timing violations

2005-08-23

2005-08-23

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S733000

Reexamination Certificate

active

06934921

ABSTRACT:
Resolving timing violations introduced by a logic built-in self test (LBIST) sub-circuit formed within an underlying integrated circuit includes analyzing a circuit path-list corresponding to the integrated circuit for timing violations and generating a circuit timing violations analysis output; generating a first LBIST/circuit path-list based on the circuit path-list and an LBIST path-list corresponding to the LBIST sub-circuit; analyzing the first LBIST/circuit path-list for timing violations and generating an LBIST/circuit timing violations analysis output; comparing the LBIST/circuit timing violations analysis output with the circuit timing violations analysis output; generating an LBIST/circuit constraint file based on the comparison and predetermined protocols; and generating a second LBIST/circuit path-list based on the circuit path-list, the LBIST path-list and the constraints file. In this way, timing problems are quickly and efficiently resolved.

REFERENCES:
patent: 5912901 (1999-06-01), Adams et al.
J. Koehl et al., A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset, Proceedings of the Conference on Design, Automation and Test in Europe, pp. 312-320, Feb. 1998.
M. Cogswell et al., Test Structure Verification of Logical BIST: Problems and Solutions, Proceedings of the ITC International Test Conference, pp. 123-130, Oct. 2000.
Gu et al., “A Fast Timing Closure Technique for Industrial Use of Logic BIST”, May 2001, pp. 1-10.
Hetherington et al., “Logic BIST for Large Industrial Designs: Real Issues and Case Studies”, ITC International Test Conference, 1999, pp. 358-367.
Nakao et al., “Low Overhead Test Point Insertion for Scan-Based BIST”, 1999, pp. 348-357.
Cheng et al., “Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST”, 1995, pp. 506-514.

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