Reset manager

Details Reset manager Reset manager

2004-11-12

2009-02-10

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07490311

ABSTRACT:
A reconfigurable module in a programmable logic device (“PLD”), such as a field-programmable gate array (“FPGA”), is reset after reconfiguration by an internal reset signal. The internal reset signal allows other modules in the PLD to remain active while the reconfigurable module is reconfigured and reset. The internal reset signal is generated by a reset manager circuit that optionally resides within the reconfigurable module.

REFERENCES:
patent: 6573748 (2003-06-01), Trimberger
patent: 2005/0007027 (2005-01-01), Fryer et al.
patent: 2005/0062703 (2005-03-01), Lee et al.
patent: 2005/0085948 (2005-04-01), Herr et al.
Lim, Davin et al., “Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulators,” Application Note XAPP290 (v1.0), May 17, 2002, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, USA.

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