Representing the design of a sub-module in a hierarchical...

Details Representing the design of a sub-module in a hierarchical... Representing the design of a sub-module in a hierarchical...

2006-09-05

2006-09-05

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07103863

ABSTRACT:
A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

REFERENCES:
patent: 3599008 (1971-08-01), Gorski-Popiel
patent: 5278105 (1994-01-01), Eden et al.
patent: 5349542 (1994-09-01), Brasen et al.
patent: 5629860 (1997-05-01), Jones et al.
patent: 5644498 (1997-07-01), Joly et al.
patent: 5822214 (1998-10-01), Rostoker et al.
patent: 5835380 (1998-11-01), Roethig
patent: 5878053 (1999-03-01), Koh et al.
patent: 5920484 (1999-07-01), Nguyen et al.
patent: 6072945 (2000-06-01), Aji et al.
patent: 6145117 (2000-11-01), Eng
patent: 6202191 (2001-03-01), Filippi et al.
patent: 6209123 (2001-03-01), Maziasz et al.
patent: 6216252 (2001-04-01), Dangelo et al.
patent: 6253359 (2001-06-01), Cano et al.
patent: 6292927 (2001-09-01), Gopisetty et al.
patent: 6345378 (2002-02-01), Joly et al.
patent: 6360350 (2002-03-01), Gabele et al.
patent: 6418551 (2002-07-01), McKay et al.
patent: 6430729 (2002-08-01), Dewey et al.
patent: 6438729 (2002-08-01), Ho
patent: 6457160 (2002-09-01), Graef et al.
patent: 6473891 (2002-10-01), Shively
patent: 6499131 (2002-12-01), Savithri et al.
patent: 6526549 (2003-02-01), You
patent: 6530066 (2003-03-01), Ito et al.
patent: 6532574 (2003-03-01), Durham et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
patent: 6615395 (2003-09-01), Hathaway et al.
patent: 6622291 (2003-09-01), Ginetti
patent: 6625611 (2003-09-01), Teig et al.
patent: 6671866 (2003-12-01), Arsintescu
patent: 6704697 (2004-03-01), Berevoescu et al.
patent: 6732340 (2004-05-01), Akashi
patent: 6799153 (2004-09-01), Sirichotiyakul et al.
patent: 6865721 (2005-03-01), Dahl et al.
patent: 6876961 (2005-04-01), Marshall et al.
patent: 7016820 (2006-03-01), Kimura et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2001/0018757 (2001-08-01), Morikawa
patent: 2002/0059553 (2002-05-01), Eng
patent: 2002/0087940 (2002-07-01), Greidinger et al.
patent: 2002/0112212 (2002-08-01), Cohn et al.
patent: 2002/0112220 (2002-08-01), Miller
patent: 2002/0133791 (2002-09-01), Cohn et al.
patent: 2002/0174409 (2002-11-01), Cohn et al.
patent: 2002/0194575 (2002-12-01), Allen et al.
patent: 2004/0128636 (2004-07-01), Ishikura
patent: 2004/0225991 (2004-11-01), Fitzhenry et al.
patent: 2006/0053396 (2006-03-01), Eng
patent: 0 809 736 (1997-11-01), None
patent: WO 96/23263 (1996-08-01), None
patent: WO 00/39717 (2000-07-01), None
PCT US02/18424, Oct. 10, 2003, PCT Search Report.
Kamon, et al. “Interconnect parasitic extractioon in the digital IC design methodology” (IEEE, May 1999, 0-7803-5832-5/99; pp. 223-230).
DeepChip.com; “Two users question PrimeTime on its interface logic models (ILMs)” ; (Sep. 19, 2001), pp. 1-2.
DeepChip.com; J. Cooley, ESNUG topics; (Oct. 25, 2001), pp. 1-20.
R. Goering, “Models speed Synopsys timing analysis” ; (Nov. 27, 2001) www.eedesign.com, pp. 1-2.
“Hierarchical scan synthesis methodology using test models”; Synopsys, Inc. 2001, Oct. 2001, pp. 1-7.
A. Daga, “Automated timing model generation”; DAC 2002 New Orleans, LA, Jun. 10-14, 2002, (pp. 146-151).
Synopsys Product Guide 04: success one chip at a time; Synopsys Inc., Mountain View, CA 2003, 2004, 24 pages.
“Synopsys offers a complete static timing and signal integrity analysis solution for nanometer system-on-chip designs,” Synposys Inc., Mountain View, CA, 2003, pp. 1-5.
J. Cooley, Synopsys PrimeTime-Sitting Pretty, DEEPCHIP, www.deepchip.com, (Mar. 28, 2001).
Cadence Design Systems, Inc., Cadence Integration Ensemble, www.cadence.com/whitepapers/ie whitepaper, (2001).
Synopsis, Inc., Hierarchical Static Timing Analysis Using Interface Logic Models, www.synopsys.com/products/analysis/pt static timing wp, (2001), Jan. 2001.

Affiliated with

Also associated with

Rating

Representing the design of a sub-module in a hierarchical... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Representing the design of a sub-module in a hierarchical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Representing the design of a sub-module in a hierarchical... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3601592