Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2008-07-07
2011-12-20
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S104000, C703S016000
Reexamination Certificate
active
08082527
ABSTRACT:
Methods are provided for compactly representing behaviors of a processor of packets. A declarative description of the processor is input. The declarative description specifies rules for manipulating the packets. A dependency graph is generated from the declarative description. The dependency graph specifies each rule that depends upon another one or more of the rules. The declarative description and the dependency graph are transformed into a Petri net representing the behaviors of the processor. The Petri net includes respective transitions for the rules and places for enabling the transitions to fire. A specification of the Petri net is output. The Petri net represents the behaviors of the processor.
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Cartier Lois D.
Kik Phallaka
Maunu LeRoy D.
Xilinx , Inc.
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