Reducing cell library development cycle time
Reducing clock skew in clock gating circuits
Reducing clock skew in clock gating circuits
Reducing coupling between wires of an electronic circuit
Reducing critical cycle delay in an integrated circuit...
Reducing datapath widths by rebalancing data flow topology
Reducing datapath widths responsively to upper bound on...
Reducing design execution run time bit stream size for...
Reducing equivalence checking complexity using inverse function
Reducing I/O supply noise with digital control
Reducing susceptibility of circuit designs to single event...
Reducing time to design integrated circuits including...
Reducing time to measure constraint parameters of components...
Reducing variation in randomized nanoscale circuit connections
Reducing verification time for integrated circuit design...
Reduction of cross-talk noise in VLSI circuits
Reduction of process antenna effects in integrated circuits
Reduction of storage elements in synthesized synchronous...
Reduction of storage elements in synthesized synchronous...
Reduction of XOR/XNOR subexpressions in structural design...