Polygonal vias
Porosity aware buffered steiner tree construction
Port assignment in hierarchical designs by abstracting macro...
Post processor for optimizing manhattan integrated circuits...
Post-layout optimization in integrated circuit design
Post-manufacture signal delay adjustment to solve...
Post-placement residual overlap removal method for core-based PL
Post-placement timing optimization of IC layout
Post-routing power supply modification for an integrated...
Post-silicon test coverage verification
Post-silicon test coverage verification
Power aware asynchronous circuits
Power bus and method for generating power slits therein
Power bus and method for generating power slits therein
Power decoupling circuit generating system and power...
Power distribution network of an integrated circuit
Power estimation based on power characterizations
Power estimation employing cycle-accurate functional...
Power estimation in high-level modeling systems
Power gating logic cones