Post-placement timing optimization of IC layout

Details Post-placement timing optimization of IC layout Post-placement timing optimization of IC layout

2006-11-14

2006-11-14

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07137093

ABSTRACT:
When an IC layout is to include time-constrained signal paths, a placement plan defining positions of cells forming the IC is analyzed to estimate lengths of nets needed to interconnect the cells based on the positions of cells included in those signal paths. A capacitance and resistance of each net is then estimated based on its estimated length. The delay through each time-constrained signal path is then estimated based on the estimated capacitance and resistance of each net to be included in the time-constrained signal path and on the terminal impedances, switching speeds and driving strengths of the cells included in the signal path. The estimated path delay for each signal path is then compared to its timing constraint to determine whether that signal path is a “critical signal path” likely to fail to meet its timing constraint following development of a detailed routing plan. A non-linear programming technique is then employed to determine how, with minimal disturbance to the placement plan, to reposition cells forming the critical paths so that when the nets are routed between the cells, all critical paths will be more likely to satisfy their timing constraints.

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R. Fletcher,Practical Methods of Optimization Second Edition, John Wiley & Sons, reprinted Mar. 1991, chapter 12.

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