Post-silicon test coverage verification

Details Post-silicon test coverage verification Post-silicon test coverage verification

2008-05-13

2008-05-13

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07373619

ABSTRACT:
In one embodiment, the invention is directed to a method of optimizing post-silicon test coverage for a system under test (“SUT”). The method comprises defining coverage data comprising Hardware Description Language (“HDL”) events; testing the SUT using a system exerciser connected to the SUT; comparing the results of the testing with the coverage data to identify underutilized areas of functionality of the SUT; and responsive to the comparing operation, performing additional tests.

REFERENCES:
patent: 6594816 (2003-07-01), Hauck
patent: 2001/0010091 (2001-07-01), Noy
patent: 2002/0002698 (2002-01-01), Hekmatpour
patent: 2003/0121011 (2003-06-01), Carter
patent: 2003/0182642 (2003-09-01), Schubert et al.
patent: 2004/0204912 (2004-10-01), Nejedlo et al.
Bart Vermeulen and Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.

Affiliated with

Also associated with

Rating

Post-silicon test coverage verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Post-silicon test coverage verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post-silicon test coverage verification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2774678