Post-layout optimization in integrated circuit design

Details Post-layout optimization in integrated circuit design Post-layout optimization in integrated circuit design

2006-09-19

2006-09-19

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07111268

ABSTRACT:
A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.

REFERENCES:
patent: 6249902 (2001-06-01), Igusa et al.
patent: 6782520 (2004-08-01), Igusa et al.
patent: 6871336 (2005-03-01), Anderson
patent: 2001/0049814 (2001-12-01), Matsumoto et al.
patent: 2003/0009734 (2003-01-01), Burks et al.
Vaughn Betz, Jonathan Rose; “FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density”; 10 pages.
Dijkstra, E. ; A Note on Two Problems in Connexion with Graphs, Numerische Mathematik 1; 1959; 2 pages. [attached publication from book: 25.2 Dijkstra's algorithm—pp. 527-531.
L. McMurchie, C. Ebeling; “PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs”; Proc. of the Feb. 1995; 1995 ACM Third International Symposium on Field-Programmable Gate Arrays Aided Design; 7 pages.
C. Changfan, Yu-Chin Hsu, Fur-Shing Tsai; “Timing Optimization on Routed Designs with Incremental Placement and Routing Characterization”; IEEE Transactions on computer-Aided Design of Integrated Circuits and Systems; vol. 19, No. 2; Feb. 2000; pp. 188-196.
Amir H. Ajami, Massoud Pedram; “Post-Layout Timing-Driven Cell Placement Using an Accurate Net Length Model with Movable Steiner Points”; ASIA South Pacific DAC; Copyright 2001; pp. 595-600.
Konrad Doll, Frank M. Johannes, Kurt J. Antreich; “Iterative Placement Improvement by Network Flow Methods”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; vol. 13, No. 10; Oct. 1994; pp. 1189-1200.

Affiliated with

Also associated with

Rating

Post-layout optimization in integrated circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Post-layout optimization in integrated circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post-layout optimization in integrated circuit design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3545991