Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-19
2003-02-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06519741
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a power decoupling circuit generating system and a power decoupling circuit generating method adapted to automatically generate a power decoupling circuit for a device such as an LSI, aiming at prevention of passage of high frequency noise to a power plane.
PRIOR ART
Since the control of electromagnetic radiation on electric products is tough or very severe, samples of products are repeatedly measured and adjusted. It takes much time and the cost is so high. The cause of electromagnetic radiation in electric products is being tracked down and measures against the electromagnetic radiation at the designing stage of a printed board are being studied.
In the tracking down of the cause of the electromagnetic radiation and study of the measures, for example, a method of using electromagnetic radiation simulation is also being examined but a problem such that the method is not practical in terms of simulation accuracy and execution time arises.
Paying attention to resonance between the ground and a power plane as a large factor of electromagnetic radiation of a printed board, power decoupling methods of interrupting oscillation in a voltage and a current from a power supply terminal of a device such as an LSI as a cause of the resonance are being developed.
As an example of such methods, Japanese Patent Publication No. 2970660 discloses a technique that a &pgr;-type low pass filter as a power decoupling circuit in the form of a capacitor, a wire (inductance), and a capacitor is disposed between a power supply terminal of a device such as an LSI and a power plane.
The &pgr;-type low pass filter is provided, for example, as shown in an equivalent circuit of
FIG. 5
, between a power supply terminal
3
A
2
of a device
3
A
1
such as an LSI and a power plane and is constructed by decoupling capacitors
3
C
1
and
3
C
2
and an inductance
3
B
1
.
By providing a line having a component equivalent to the inductance
3
B
1
between the decoupling capacitors
3
C
1
and
3
C
2
, a filter construction is obtained.
In the above-described prior art, however, it is necessary to calculate a line width and a line length of the line to realize the inductance
3
B
1
for each circuit constructing the &pgr;-type low pass filter as a power decoupling circuit. In the inductance
3
B
1
necessary for the device
3
A
1
such as an LSI, after providing a line with calculated line width and line length, it is necessary to manually dispose the decoupling capacitors
3
C
1
and
3
C
2
constructing the &pgr;-type low pass filter.
There is consequently a problem such that generation (designing) of a power decoupling circuit is extremely complicated.
SUMMARY OF THE INVENTION
The invention has been achieved in consideration of such circumstances and its object is to provide a power decoupling circuit generating system and power decoupling circuit generating method capable of easily generating a power decoupling circuit for each device such as an LSI.
According to the first aspect of the invention, there is provided a power decoupling circuit generating system having: a power decoupling circuit generating unit for generating a power decoupling circuit of a &pgr;-type low pass filter construction having first and second decoupling capacitors to be added to a power supply terminal of a device as a target from which high frequency noise is prevented from being passed to a power plane and a power line corresponding to an inductance; and information holding means for holding information regarding parameters of generating the power decoupling circuit, wherein the power decoupling circuit generating means automatically generates a power decoupling circuit to be added to the power supply terminal of the device on the basis of the information of the information holding means.
The power decoupling circuit generating unit can have: a power supply terminal information setting unit for selecting a power supply terminal of the device and adding parameters of generating the power decoupling circuit to the power supply terminal on the basis of the information of the information holding means; a power line calculating unit for calculating a line width and a line length of the power line in the power decoupling circuit; and a decoupling circuit arranging unit for laying the power line based on the calculated line width and line length, disposing the first decoupling capacitor based on the parameters added by the power supply terminal information setting unit to the power supply terminal side of the power line, and disposing the second decoupling capacitor on the side opposite to the power supply terminal of the power line.
The information holding means can have: a capacitor parts library in which shapes of capacitor parts of the first and second decoupling capacitors to be added and frequency characteristics of the capacitor parts are defined; and a line calculation parameter file in which a dielectric constant of a material used for an insulator of a printed board on which the device is mounted and a layer configuration of the printed board are defined.
In the capacitor parts library, information indicative of a series inductance and a series resistance of the capacitor part itself, an inductance of a pad for mounting the capacitor, and an inductance of a via hole for connecting the pad and a power layer and a ground layer on the inside can be included. In the line calculation parameter file, information indicative of a ratio between a characteristic impedance of the power line and impedances of the first and second decoupling capacitors can be included.
At the time of calculating a line width and a line length of the power line, the power line calculating unit can use an operating frequency of the device as a target set by the power supply terminal information setting unit, characteristics of the first and second decoupling capacitors constructing the power decoupling circuit, a dielectric constant of an insulator of a printed board defined in the line calculation parameter file, and layer configuration information of the printed board.
When parameters of generating the power decoupling circuit are added to the power supply terminal, the power supply terminal information setting unit can select a capacitor having a parasitic inductance as small as possible, defined in the capacitor parts library.
The power supply terminal information setting unit can add parameters of generating the power decoupling circuit to a plurality of power supply terminals of the device on the basis of the information in the information holding means, the power line calculating unit can calculate a line width and a line length of the power line laid among the plurality of power terminals, and the decoupling circuit arranging unit can lay the power line based on the calculated line width and line length and dispose, in addition to the first and second decoupling capacitors based on the parameters added by the power supply terminal information setting unit, third and fourth decoupling capacitors to the power supply terminal side on which the first and second decoupling capacitors are not disposed.
According to the tenth aspect of the invention, there is provided a power decoupling circuit generating method including: a first step of generating a power decoupling circuit of a &pgr;-type low pass filter construction having first and second decoupling capacitors to be added to a power supply terminal of a device as a target from which high frequency noise is prevented from being passed to a power plane and a power line corresponding to an inductance by a power decoupling circuit generating unit; and a second step of holding information regarding parameters of generating the power decoupling circuit in information holding means, wherein a power decoupling circuit to be added to the power supply terminal of the device is automatically generated by the power decoupling circuit generating means on the basis of the information of the information holding means.
The first step can include: a third st
Asao Kiyoshi
Harada Takashi
Sasaki Hideki
Yaguchi Takahiro
Lin Sun James
NEC Corporation
Siek Vuthe
Young & Thompson
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