Post-manufacture signal delay adjustment to solve...

Details Post-manufacture signal delay adjustment to solve... Post-manufacture signal delay adjustment to solve...

2000-08-17

2003-03-11

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06532574

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to integrated circuit design and in particular to minimizing capacitive coupling signal delays in integrated circuit designs. Still more particularly, the present invention relates to post-manufacture adjustment of signal arrival times to reduce capacitive coupling signal delays.
2. Description of the Related Art
As feature sizes within integrated circuits shrink, architectures grow more complex, and higher operating speeds are sought, integrated circuit designers face increasing issues in meeting performance objectives. Many problems once thought minor in importance or rare in occurrence are becoming more significant and/or pronounced.
One such problem is on-chip noise. Noise may take various forms and cause varying effects. Some common forms of noise are power supply droop and localized power variations, signal line coupling, and Miller effect capacitances across circuit inputs/outputs. Some common effects of such noise are reduced or varying design performance, latch (memory) state loss, and signal propagation variation. A more subtle effect of noise, however, is change in signal delay due to capacitive coupling. That is, a given signal line routed adjacent to other signal lines creates, as a result of the metallurgical manufacturing process, a capacitor between those signal lines.
FIG. 8
illustrates the capacitance formed between adjacent signal lines. In the example shown, Signal
2
has two adjacently routed signal lines or interconnects, Signal
1
and Signal
3
, which add to the net capacitance of the conductor. This capacitance due to adjacent signal lines, denoted C
adj
, is in addition to the vertical capacitive components and any sink (gate) capacitance, which is collectively denoted C
base
in FIG.
8
. The capacitance of the signal line Signal
2
due to the additional capacitance C
adj
from adjacent signal lines may be significantly greater than would be seen for the interconnect Signal
2
without adjacent signal lines Signal
1
and Signal
3
.
The capacitance of signal line Signal
2
(denoted C
signal2
) varies under different switching conditions. The amount of capacitance contributed to the total capacitance C
signal2
seen by signal line Signal
2
by an adjoining signal lines depends on whether the adjoining signal lines switch state, and in which direction (i.e., rising or falling) relative to switching within signal line Signal
2
. Assuming that the adjacent signal lines Signal
1
and Signal
3
arrive (are driven) at the same time and rise/fall at the same slew rate, there are three different possible capacitances for each adjacent signal line which may be contributed to the total capacitance C
signal2
. If the adjacent signal line does not switch state (i.e., is “quiet”), then the capacitive contribution of the adjacent signal line is C
adj
. A first order approximation of the total capacitance C
signal2
seen by signal line Signal
2
under different possible switching conditions is set forth in Table I.
TABLE I
Signal 1
Signal 2
Signal 3
C
signal2
Quiet
Rising
Quiet
C
base
+ 2*C
adj
Quiet
Falling
Quiet
C
base
+ 2*C
adj
Quiet
Rising
Rising
C
base
+ *C
adj
Quiet
Falling
Falling
C
base
+ C
adj
Quiet
Rising
Falling
C
base
+ 3*C
adj
Quiet
Falling
Rising
C
base
+ 3*C
adj
Rising
Rising
Quiet
C
base
+ C
adj
Falling
Falling
Quiet
C
base
+ C
adj
Falling
Rising
Quiet
C
base
+ 3*C
adj
Rising
Falling
Quiet
C
base
+ 3*C
adj
Rising
Rising
Falling
C
base
+ 2*C
adj
Rising
Falling
Falling
C
base
+ 2*C
adj
Falling
Rising
Rising
C
base
+ 2*C
adj
Falling
Falling
Rising
C
base
+ 2*C
adj
Rising
Rising
Rising
C
base
Falling
Falling
Falling
C
base
Rising
Falling
Rising
C
base
+ 4*C
adj
Falling
Rising
Falling
C
base
+ 4*C
adj
If the adjacent signal line switches state in the same direction as signal line Signal
2
(i.e., both rising or both falling), then no charge is required to counteract the adjacent capacitance and the capacitive contribution of the adjacent signal line is essentially zero. If the adjacent signal line switches state in the opposite direction as signal line Signal
2
(i.e., rising rather than falling or falling rather than rising), then twice as much charge is required to counteract the adjacent capacitance and the capacitive contribution of the adjacent signal line is
2
*C
adj
.
During timing analysis, capacitive effects of neighboring conductors are relatively simple to offset by increasing or decreasing the net capacitance due to adjacency in order to account for latest/earliest possible effects. For example, increasing the total capacitance due to worst-case adjacent signal line switching may be performed after the capacitance calculation, then utilized in the timing run. However, this depends heavily on reliably predicting the arrival times and slew rates for signals on all neighboring signal lines. Since changing the total capacitance due to such switching characteristics depends on the total capacitance, the process is iterative in nature. That is, timing calculations prior to increasing the capacitance are not longer accurate in terms of arrival times and slew rates after the increase because of loading changes associated with the increase.
Although calculating switching capacitance effects appears simple for a case such as that shown in
FIG. 8
, in complex designs such as superscalar processors a signal line may have any number of adjacent signal lines (well beyond the two shown in
FIG. 8
) with a sufficiently significant capacitive coupling value to induce delay variations. When also accounting for all possible signal arrival and slew miscalculations (due to static timing analysis assumptions, inaccurate circuit timing models, interconnect modeling approximations, parasitic extraction inaccuracy, etc.) and all process variations (e.g., interconnect width/spacing variation leading to significant variation in coupling capacitance values), iteratively processing the results through multiple timing runs is essentially impossible.
These problems have resulted in two design approaches. The first approach simply doubles all coupling capacitances above a set tolerance for all signal lines in a design. This approach is overly pessimistic and leads to overdesign of the circuitry, and also tends to create a slower than optimal design because many circuits are redesigned to provide increased drive strength to counteract the expected additional loading. A larger driver creates a larger gate capacitance on the source, which necessitates a larger circuit and/or slower perormance. This, in turn, can lead to slower than expected results on the actual manufactured design, resulting in decreased design performance as well as increased design time.
The second approach ignores the effects altogether, which leads to slower than expected results on the actual manufactured design and decreased design performance, but reduces design time. Fixing any noise induced delay problems requires new mask designs and new chips, although more often than the alternate approach.
It would be desirable, therefore, to eliminate the coupling induced delay variation on the design post-manufacture, following the second approach and using existing manufactured chips at the highest possible frequency. In addition, any problems not properly accounted for in the first approach could also be solved, again providing use of existing chips at a higher performance.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide improved integrated circuit designs.
It is another object of the present invention to minimize capacitive coupling signal delays in integrated circuit designs.
It is yet another object of the present invention to provide post-manufacture adjustment of signal arrival times to reduce capacitive coupling signal delays.
The foregoing objects are achieved as is now described. Adjacent signal lines within the critical path of logic within an integrated circuit are

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