Enhanced hardware debugging with embedded FPGAS in a...

Enhanced incremental placement during physical synthesis

Enhanced programmable core model with integrated graphical...

Enhanced verification by closely coupling a structural...

Enhanced verification by closely coupling a structural...

Enhanced verification through binary decision diagram-based...

Enhanced verification through binary decision diagram-based...

Enhancement of performance of a conductive wire in a...

Enhancing a power distribution system in a ceramic...

Enhancing formal design verification by reusing previous...

Enhancing mergeability of datapaths and reducing datapath...

Equivalence checking of scan path flush operations

Error detection in dynamic logic circuits

Error portion detecting method and layout method for...

ESD analysis device and ESD analysis program used for...

ESD design, verification and checking system and method of use

Estimating capacitance effects in integrated circuits using...

Estimating capacitances using information including feature...

Estimating current density parameters on signal leads of an...

Estimating free space in IC chips