Error portion detecting method and layout method for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000, C702S069000, C702S079000, C702S065000, C703S016000, C703S019000, C324S523000, C324S532000, C324S537000

Reexamination Certificate

active

10751523

ABSTRACT:
For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.

REFERENCES:
patent: 5047967 (1991-09-01), Sander et al.
patent: 5903476 (1999-05-01), Mauskar et al.
patent: 6311147 (2001-10-01), Tuan et al.
patent: 6345379 (2002-02-01), Khouja et al.
patent: 6370674 (2002-04-01), Thill
patent: 6453443 (2002-09-01), Chen et al.
patent: 6480815 (2002-11-01), Olson et al.
patent: 6615395 (2003-09-01), Hathaway et al.
patent: 2003/0212538 (2003-11-01), Lin et al.
patent: 2003/0226122 (2003-12-01), Hathaway et al.
patent: 2006/0095872 (2006-05-01), McElvain et al.
patent: 7-239865 (1995-09-01), None
Bobba et al., “Simultaneous Switching Noise in CMOS VLSI Circuits”, 1999 Southwest Symposium on Mixed-Signal Design, Apr. 11, 1999, pp. 15-20.
Takaki Yoshida et al., “A New Approach for Low Power Scan Testing”, ITC International Test Conference, 2003, IEEE, pp. 480-487.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Error portion detecting method and layout method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Error portion detecting method and layout method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error portion detecting method and layout method for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3762476

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.