Error detection in dynamic logic circuits

Details Error detection in dynamic logic circuits Error detection in dynamic logic circuits

2005-10-11

2005-10-11

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06954912

ABSTRACT:
Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

REFERENCES:
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6556962 (2003-04-01), Patra
patent: 2003/0042933 (2003-03-01), Hill et al.
Srivastava, Pranjal, et al.; “Issues in the Design of Domino Logic Circuits”; Proceedings of the 8thGreat Lakes Symposium on VLSI, Lafayette, Louisiana, U.S.A.; Feb. 19-21, 1998; pp. 108-112.
Wang, Zhongde, et al.; “Fast Address Using Enhanced Multiple-Output Domino Logic”; IEEE Journal of Solid-State Circuits, vol. 32, No. 2, Feb. 1997; pp. 206-214.

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