Enhanced incremental placement during physical synthesis

Details Enhanced incremental placement during physical synthesis Enhanced incremental placement during physical synthesis

2006-02-24

2008-09-23

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07428718

ABSTRACT:
A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.

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patent: 2006/0190224 (2006-08-01), Allen et al.
U.S. Appl. No. 11/361,370, filed Feb. 24, 2006, Singh, Amit, et al., entitled “Incremental Placement During Physical Synthesis”, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

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