Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-03
2010-12-14
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000
Reexamination Certificate
active
07853909
ABSTRACT:
An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.
REFERENCES:
patent: 6445039 (2002-09-01), Woo et al.
patent: 6770938 (2004-08-01), Fliesler et al.
patent: 6963110 (2005-11-01), Woo et al.
patent: 7719083 (2010-05-01), Chang
patent: 2008/0036037 (2008-02-01), Woo et al.
patent: 2008/0036536 (2008-02-01), Khorramabadi
patent: 2008/0174925 (2008-07-01), Woo et al.
patent: 2010/0172060 (2010-07-01), Woo et al.
patent: 2004-282058 (2004-10-01), None
patent: 2005-196468 (2005-07-01), None
Beebe, “Methodology for Layout Design and Optimization of ESD Protection Transistors”, Proceedings of Electrical Overstress/Electrostatic Discharge Symposium, Sep. 10-12, 1996, pp. 265-275.
Mohan et al., “Modeling ESD Protection”, IEEE Potentials, vol. 24, No. 1, Feb.-Mar. 2005, pp. 21-24.
Ziman et al., “Simulation and Measurement of EM Fields Caused by Electrostatic Discharges”, IEE Colloquium on ESD (Electrostatic Charge) and ESD Counter Measures, Mar. 28, 1995, pp. 5/1-5/6.
Hirata Morihisa
Katou Tetsuya
Kitayama Tomohiro
Kobayashi Susumu
Okushima Mototsugu
Foley & Lardner LLP
Kik Phallaka
Renesas Electronics Corporation
LandOfFree
ESD analysis device and ESD analysis program used for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with ESD analysis device and ESD analysis program used for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD analysis device and ESD analysis program used for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4198427