IC layout optimization to improve yield
IC layout physical verification method
IC layout system employing a hierarchical database by...
IC layout system having separate trial and detailed routing...
IC layout with non-quadrilateral Steiner points
IC layouts with at least one layer that has more than one...
IC package similar IDE interface solid state disk module and...
IC signal path resistance estimation method
IC substrate noise modeling including extracted capacitance...
IC substrate noise modeling with improved surface gridding...
IC tiling pattern method, IC so formed and analysis method
IC timing analysis with known false paths
Identification and implementation of clock gating in the...
Identification of an integrated circuit from its physical...
Identifying high E-field structures
Identifying line width errors in integrated circuit designs
Identifying parasitic diode(s) in an integrated circuit...
Identifying phantom images generated by side-lobes
Identifying specific netlist gates for use in code coverage...
IEEE 1394 cable connector with short circuit switch