Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-04
2006-04-04
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C707S793000, C707S793000
Reexamination Certificate
active
07024644
ABSTRACT:
Diffusion effects during an IC fabrication process cause actual dimensions of adjacent conductors in an IC to vary from nominal dimensions specified by data defining the IC layout. A computer-aided design tool processes the layout data to generate a separate database for each layer of the IC, including a separate table corresponding to each grid line of that layer. Each table includes a separate table entry corresponding to each conductor to reside along the table's corresponding grid line, each table entry indicating nominal dimensions and position of its corresponding conductor. The tool sorts grid line tables within each layer's database in an order in which their corresponding grid lines are arranged on that layer, and sorts entries in each table in an order in which their corresponding conductors are to appear along the table's corresponding grid line. The tool then reads each entry in each table of each database only once, in the orders in which the entries and tables are sorted, to obtain information it needs to estimate actual dimensions of each conductor, and estimates the resistance of each conductor as a function of its estimated actual dimensions.
REFERENCES:
patent: 5552718 (1996-09-01), Bruce et al.
patent: 6360350 (2002-03-01), Gabele et al.
patent: 2003/0237063 (2003-12-01), Kauth et al.
Bedell Daniel J.
Cadence Design Systems Inc.
Siek Vuthe
Smith-Hill and Bedell
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