Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-31
2002-08-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06438733
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to substrate modeling. More particularly, the present invention relates to modeling characteristics of a substrate using doping profiles.
2. Description of the Related Art
Integrated circuits are typically modeled, or simulated, prior to fabrication. These simulation tools may be used to optimize performance of integrated circuits as well as reduce the likelihood of failure of such circuits after fabrication. Thus, simulation is advantageous since circuits may be easily redesigned without duplicative fabrication costs.
Simulation tools are typically used to model the behavior of transistor devices that are formed on a substrate as well as interconnect lines that connect these devices. However, through the use of such tools, only a portion of the substrate is modeled. By way of example, during simulation of a transistor device formed on a substrate approximately 400 microns thick, a thickness of approximately 0.1 microns is typically modeled. Since net doping levels vary throughout the substrate, modeling only a fraction of the substrate yields an inaccurate simulation of the substrate characteristics. Accordingly, it would be desirable if the entire depth of the substrate were modeled.
Further, a substrate is not an ideal medium. Since recently developed fabrication processes permit device feature sizes to be reduced, the frequency of operation for transistor devices has increased with these developments. Similarly, with such a reduction in device feature size, the distance between transistor devices may be reduced. Since noise attenuates with the distance between the source of the noise (e.g., power supply) and the receiver of the noise, this parasitic noise may easily propagate to multiple devices. As a result, this parasitic noise may prevent these transistor devices from operating correctly. More particularly, these negative consequences may be considerable for sensitive semiconductor devices such as MOS transistors. Thus, it would be desirable if substrate modeling could be performed to detect this noise.
Noise may be transferred to the substrate by a circuit formed on the surface of the substrate. This noise transfer may occur at various interfaces between the circuit and the substrate. A circuit typically includes numerous devices connected by conductive interconnect lines. Capacitance as well as resistance between the substrate and an overlying interconnect line or device may create undesirable parasitic effects. As a result, this parasitic noise may be transferred through the substrate to other devices in the circuit. Thus, it would be desirable to model the interface between the substrate and the circuit.
IC, substrates, as well as portions of the substrates, are typically doped. By way of example, portions of substrates may be doped to create device elements, such as source and drain diffusion regions. Thus, substrates commonly include multiple layers that contain various net doping levels. In addition, the resistance present in the substrate varies with these net doping levels. These varied resistances affect the current flow throughout the substrate and therefore the performance of integrated circuits formed on the substrate. Thus, it would be desirable if these doping levels could be considered during the substrate modeling.
In view of the above, it would be desirable if a system and method for modeling substrate noise through varying doping levels were developed. In this manner, noise flowing through the substrate as well as between the substrate and devices formed on the substrate, may be modeled and eliminated. Accordingly, a circuit may be designed to eliminate or reduce this noise at the design phase without estimation or fabrication of the circuit.
SUMMARY OF THE INVENTION
An invention is described herein which provides methods and apparatus for modeling noise present in an integrated circuit substrate. This is accomplished by obtaining a doping profile associated with the integrated circuit substrate. Through vertically discretizing the doping profile, the doping profile is divided into a finite number of discrete portions. Moreover, all doping profiles associated with the integrated circuit substrate may be obtained and vertically discretized. The integrated circuit substrate can then be modeled using one or more vertically discretized doping profiles. In this manner, speed and accuracy may be balanced during the modeling process.
According to one aspect of the invention, an integrated circuit substrate is modeled by using an associated doping profile. A position on a surface of the integrated, circuit substrate is obtained. A combination of layers associated with the position and defining a vertical column beneath the position is obtained. A doping profile associated with the combination of layers is obtained. The doping profile includes a plurality of portions, each of which is associated with a different range of substrate depth. A model of the substrate may then be generated using the obtained doping profile. Such modeling may similarly be performed using a set of doping profiles.
According to another aspect of the invention, methods and apparatus for characterizing an integrated circuit substrate are disclosed. A set of one or more substrate doping profiles including a net doping level for each one of a plurality of depths within an integrated circuit substrate is obtained. A set (e.g., combination) of layers associated with the set of one or more substrate doping profiles is determined. The set of layers is in an order in relation to a surface of the integrated circuit substrate. By way of example, the set of layers may be sorted with respect to the sequence in which the layers are used during the fabrication process of an integrated circuit. The set of one or more substrate doping profiles is vertically discretized to form a vertically discretized substrate doping profile. A specific combination of layers is then associated with each vertically discretized substrate doping profile.
To simplify the number of computations required to model a high component count substrate, there is included an improved technique for performing surface gridding, which allows highly dense regions to be modeled with dense divisions while less populated regions to be modeled with larger surface divisions. As an object is introduced into the substrate, the local partition impacted is examined to determine if additional divisions are needed for proper surface modeling. As an object is removed, the local/global partitions impacted are reviewed to determine whether simplification may be performed.
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Alan Pun et al., “E
Beyer Weaver & Thomas LLP
Do Thuan
Simplex Solutions, Inc.
Smith Matthew
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