Identifying parasitic diode(s) in an integrated circuit...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07490303

ABSTRACT:
A method comprises tracing a first and second terminal of a junction through a circuit layout to associated power supplies to determine their respective defined bias values. The method further comprises comparing the defined bias values of each terminal in order to determine, based on the comparison, whether the junction is forward biased.

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